 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Preliminary TENTATIVE THNCFXXXMBA/BAI Series TOSHIBA SMALL FORM FACTOR CARD CompactFlashTM Card DESCRIPTION The THNCFXXXMBA/BAI series CompactFlashTM card is a flash technology based with ATA interface flash memory card. It is constructed with flash disk controller chip and NAND-type Toshiba flash memory device. The CompactFlashTM card operates in both 5-Volt and 3.3-Volt power supplies. It comes in capacity of 8, 16, 32, 48, 64, 96, 128, 160, 192, 256, 320, 384 and up to 512 MB unformatted for type-I card. Emulating IDE hard disk drives and being certified in accordance with the CompactFlashTM Certification Plan it is a perfect choice of solid-state mass-storage cards for battery backup handheld devices such as Digital Camera, Audio Player, PDA, or the applications that require high environment tolerance with high performance sustained write speed. FEATURES * CompactFlashTM Compatibility * * * Certified in accordance with the CompactFlashTM Certification Plan Substantially compatible with PC Card standard and PC Card ATA Support for CIS implemented with 256 bytes of attribute memory * ATA/IDE interface * * * ATA command set compatible Support for 8- or 16-bit host transfers Programmable and auto-wait-state generation for compatibility with any host speed using IORDY * High performance * * * * Supports PIO mode 4, both at 16.6 Mbytes/second theoretically Sustained write : max 1.5 Mbytes/second (8MB to 48MB), 3.2 Mbytes/second (64MB to 512MB) Sustained read : max 6.5Mbytes/second Single +5 Volt or 3.3 Volt power supply and very low power consumption with automatic power management. Notes: CompactFlashTM is a trademark of SanDisk Corporation and is licensed royalty-free to the CFA, which in turn will license it royal-free to CFA members. CFA: CompactFlashTM Association. Products Models unformatted 8MB 16MB 32MB 48MB 64MB 96MB 128MB 160MB 192MB 256MB 320MB 384MB 512MB Cylinder 248 248 496 744 978 733 978 611 733 978 814 977 993 Head 2 4 4 4 4 8 8 16 16 16 16 16 16 Sector 32 32 32 32 32 32 32 32 32 32 48 48 63 Model No. THNCF008MBA / BAI THNCF016MBA / BAI THNCF032MBA / BAI THNCF048MBA / BAI THNCF064MBA / BAI THNCF096MBA / BAI THNCF128MBA / BAI THNCF160MBA / BAI THNCF192MBA / BAI THNCF256MBA / BAI THNCF320MBA / BAI THNCF384MBA / BAI THNCF512MBA / BAI 2002-10-20 1/48 Preliminary Products Specifications * Dimensions: THNCFXXXMBA/BAI Series Type I card : 36.4mm(L) x 42.8mm (W) x 3.3mm (H) * Storage Capacities: 8,16, 32, 48, 64, 96,128, 160, 192, 256, 320, 384 and up to 512 MB (unformatted) * System Compatibility: * Performance: Please refer to the compatibility list. Supports PIO mode 4, both at 16.6 Mbytes/second theoretically Sustained write max 1.5 Mbyte/sec (max) in ATA PIO mode 4 (8MB to 48MB) Sustained write max 3.2 Mbyte/sec (max) in ATA PIO mode 4 (64MB to 512MB) Sustained read max 6.5 Mbyte/sec (max ) in ATA PIO mode 4 * Operating Voltage: 3.3V 0.3V 5.0V 0.5V * Power consumption: * 5V operation Active mode: Write operation : Read operation : Sleep mode : 3.3V operation Active mode: Write operation : Read operation : Sleep mode : 43 mA (Typ.) 35 mA (Typ.) 1.2mA (Typ) *1 2.0mA (max.) * 38 mA (Typ.) 30 mA (Typ.) 1.0mA (Typ) *1 1.5mA (max.) * Environment conditions: * * Storage temperature: Operating temperature: 0C to 70C (THNCFXXXMBA Series) Commercial grade -40C to 85C (THNCFXXXMBAI Series) Industrial grade -20C to 85C (THNCFXXXMBA Series) Commercial grade -45C to 90C (THNCFXXXMBAI Series) Industrial grade 2002-10-20 2/48 Preliminary Electrical Interface * Physical Description: THNCFXXXMBA/BAI Series The host is connected to the CompactFlashTM Storage Card using a standard 50-pin connector. The connector in the host consists of two rows of 25 male contacts each on 50 mil (1.27 mm) centers. * Pin Assignments and Pin Type: The signal/pin assignments are listed in Table 4. Low active signals have a " " prefix. Pin types are Input, Output or Input/Output. Section "Electrical specification" and "DC characteristics" defines the all input and output type structures. * Electrical Description: The CompactFlashTM Storage Card functions in three basic modes: 1) PC Card ATA using I/O Mode, 2) PC Card ATA using Memory Mode and 3) True IDE Mode, which is compatible with most disk drives. CompactFlashTM Storage Cards are required to support all three modes. The CF Cards normally function in the first and second modes, however they can optionally function in True IDE mode. The configuration of the CompactFlashTM Card will be controlled using the standard PCMCIA configuration registers starting at address 200h in the Attribute Memory space of the storage card. Or for True IDE Mode, pin 9 being grounded. The configuration of the CF Card will be controlled using configuration registers. The configuration registers are starting at the address defined in the Configuration Tuple (CISTPL_CONFIG) in the Attribute Memory space of the CF Card. Signals, whose source is the host, is designated as inputs while signals that the CompactFlashTM Storage Card sources are outputs. The CompactFlashTM Storage Card logic levels conform to those specified in the PC Card Standard Release 8. Each signal has three possible operating modes: 1) PC Card Memory mode 2) PC Card I/O mode 3) True IDE mode True IDE mode is required for CompactFlashTM Storage cards. All outputs from the card are totem pole except the data bus signals that are bi-directional tri-state 2002-10-20 3/48 Preliminary Pin Assignments and Pin Type PC Card Memory Mode Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Signal Name GND D03 D04 D05 D06 D07 I/O I/O I/O I/O I/O I I I I I I Pin Type In, Out Type Ground I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I3U I3Z I4U I3Z I3Z I3Z Power I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I3Z I3Z I3Z I3Z I3Z I3Z I3Z I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 OT1 Ground Ground I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I3U Ground I4U I4U I4U OT1 Power I O I I1U OPEN I3U Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 THNCFXXXMBA/BAI Series PC Card I/O Mode Signal Name GND D03 D04 D05 D06 D07 I/O I/O I/O I/O I/O I I I I I I Pin Type In, Out Type Ground I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I3U I3Z I4U I3Z I3Z I3Z Power I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I3Z I3Z I3Z I3Z I3Z I3Z I3Z I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 OT1 Ground Ground I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I3U Ground I4U I4U I4U OT1 Power I O I I1U OPEN I3U Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 True IDE Mode Signal Name GND D03 D04 D05 D06 D07 I/O I/O I/O I/O I/O I I I I I I 4 Pin Type In, Out Type Ground I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I3U I3Z I4U I3Z I3Z I3Z Power -CE1 A10 -CE1 A10 -CS0 A10 2 -OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 WP -OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 -ATA SEL A09 A08 2 2 2 A07 VCC A06 A05 A04 A03 2 2 2 2 I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I3Z I3Z I3Z I3Z I3Z I3Z I3Z I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 ON1 Ground Ground I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 I3U Ground I4U I4U I4U OZ1 Power A02 A01 A00 D00 D01 D02 -IOIS16 -CD2 -CD1 D11 1 1 1 1 1 1 -IOCS16 -CD2 -CD1 D11 1 1 1 1 1 1 -CD2 -CD1 D11 1 1 1 1 1 1 D12 D13 D14 D15 D12 D13 D14 D15 D12 D13 D14 D15 -CE2 -CE2 -CS1 -VS1 -IORD -IOWR -WE RDY/BSY VCC -VS1 -IORD -IOWR -WE IREQ VCC -VS1 -IORD -IOWR -WE 3 INTRQ VCC -CSEL -VS2 RESET -CSEL -VS2 RESET -CSEL -VS2 -RESET I O I I1U OPEN I3U 2002-10-20 4/48 Preliminary PC Card Memory Mode Pin 42 43 44 45 46 47 48 49 50 Signal Name Pin Type O O I I/O I/O I/O I/O I/O In, Out Type OT1 OT1 I3U I4U,OT1 I4U,OT1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 Ground Pin 42 43 44 45 46 47 48 49 50 THNCFXXXMBA/BAI Series True IDE Mode In, Out Type OT1 OT1 I3U I4U,OT1 I4U,OT1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 Ground Pin 42 43 44 45 46 47 48 49 50 Signal Name IORDY 4 PC Card I/O Mode Signal Name Pin Type O O I I/O I/O I/O I/O I/O Pin Type O O I I/O I/O I/O I/O I/O In, Out Type ON1 OZ1 I3U I4U,ON1 I4U,ON1 I4Z,OZ1 I4Z,OZ1 I4Z,OZ1 Ground -WAIT -INPACK -REG BVD2 BVD1 D08 D09 D10 1 1 1 -WAIT -INPACK -REG -SPKR -STSCHG D08 D09 1 1 1 -INPACK -REG 3 -DASP -PDIAG D08 D09 1 1 1 D10 D10 GND GND GND Notes: 1. These signals are required only for 16 bit access and not required when installed in 8 bit systems. Devices should allow for 3-state signals not to consume current. 2. Should be grounded by the host. 3. Should be tied to VCC by the host. 2002-10-20 5/48 Preliminary Signal Description Signal Name A10 to A0 (PC Card Memory Mode) A10 to A0 (PC Card I/O Mode) I THNCFXXXMBA/BAI Series Dir Pin No. Description These address lines along with the-REG signal are used to select the following: The I/O port address registers within the 8,10,11,12,1 CompactFlash Storage Card, the memory mapped port address 4,15,16,17,1 registers within the CompactFlash Storage Card, a byte in the 8,19,20 card's information structure and its configuration control and status registers. 18,19,20 In True IDE Mode only A [2 : 0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. This signal is asserted high as BVD1 is not supported This signal is asserted low to alert the host to changes in the RDY/-BSY and Write Protect states; while the I/O interface is configured .Its use is controlled by the Card Config and Status Register. In the True IDE Mode, this input/output is the Pass Diagnostic signal in the Master/Slave handshake protocol This signal is asserted high, as BVD2 is not supported. This line is the Binary Audio output from the card .If the Card does not support the Binary Audio function, this line should be held negated. In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. These Card Detect pins are connected to ground on the CompactFlash Storage Card. They are used by the host to determine that the CompactFlash Storage Card is fully inserted into its socket. These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. -CE2 always accesses the odd byte of the word. -CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2.A multiplexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on D0~D7. See Access specification below. In the True IDE Mode CS0 is the chip select for the task file registers while CS1 is used to select the Alternate Status Register and the Device Control Register. A2 to A0 (True IDE Mode) BVD1 (PC Card Memory Mode) -STSCHG (PC Card I/O Mode) I/O 46 -PDIAG (True IDE Mode) BVD2 (PC Card Memory Mode) -SPKR (PC Card I/O Mode) I/O 45 -DASP (True IDE Mode) -CD1, -CD2 (PC Card Memory Mode) -CD1, -CD2 (PC Card I/O Mode) O 26,25 -CD1, -CD2 (True IDE Mode) -CE1, -CE2 (PC Card Memory Mode) -CE1, -CE2 (PC Card I/O Mode) I 7,32 -CS0, -CS1 (True IDE Mode) -CSEL (PC Card Memory Mode) -CSEL (PC Card I/O Mode) I 39 This signal is not used for this mode. -CSEL (True IDE Mode) D15 to D00 (PC Card Memory Mode) D15 to D00 (PC Card I/O Mode) D15 to D00 (True IDE Mode) I/O This internally pulled up signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. These lines carry the Data, Commands and Status information 31,30,29,28, between the host and the controller. D00 is the LSB of the Even 27,49,48,47, Byte of the Word.D08 is the LSB of the Odd Byte of the Word. 6,5,4,3,2, True IDE Mode, all Task File operations occur in byte mode on the 23,22,21 low order bus D00 to D07 while all data transfers are 16 bit using D00 to D15. 2002-10-20 6/48 Preliminary Signal Name GND (PC Card Memory Mode) GND (PC Card I/O Mode) GND (True IDE Mode) THNCFXXXMBA/BAI Series Description Dir Pin No. 1,50 Ground -INPACK (PC Card Memory Mode) This signal is not used in this mode. The Input Acknowledge signal is asserted by the CompactFlash -INPACK (PC Card I/O Mode) Storage Card when the card is selected and responding to an I/O O 43 read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the CompactFlash Storage Card and the CPU. -INPACK (True IDE Mode) In True IDE Mode this output signal is not used and should not be connected at the host. This signal is not used in this mode. This is an I/O Read strobe generated by the host. This signal gates I 34 I/O data onto the bus from the CompcatFlash Storage Card when the card is configured to use the I/O interface. In True IDE Mode, this signal has same function as in PC Card I/O Mode. This signal is not used in this mode. The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the CompactFlash Storage Card controller registers -IORD (PC Card Memory Mode) -IORD (PC Card I/O Mode) -IORD (True IDE Mode) -IOWR (PC Card Memory Mode) -IOWR (PC Card I/O Mode) when the CompactFlash Storage Card is configured to use the I/O I 35 interface. The clocking will occur on the negative to positive edge of the signal (trailing edge) -IOWR (True IDE Mode) In True IDE Mode, this signal has the same function as in PC Card I/O Mode. This is an Output Enable strobe generated by the host interface .It is used to read data from the CompactFlash Storage Card in Memory Mode and to read the CIS and configuration registers. I 9 In PC Card I/O Mode, this signal is used to read the CIS and configuration registers. To enable True IDE Mode this input should be grounded by the host. -OE (PC Card Memory Mode) -OE (PC Card I/O Mode) -ATA SEL (True IDE Mode) 2002-10-20 7/48 Preliminary Signal Name Dir Pin No. THNCFXXXMBA/BAI Series Description In Memory Mode this signal is set high when the CompactFlash Storage Card is ready to accept a new data transfer operation and held low when the card is busy .The Host memory card socket must provide a pull-up resistor. RDY/-BSY (PC Card Memory Mode) At power up and at Reset the RDY/-BSY signal is held low (busy) until the CompactFlash Storage Card has completed its power up or reset function. No access of any type should be made to the CompactFlash Storage Card during this time .The RDY/-BSY signal is held high (disabled from being busy) whenever the following condition is true. The CompactFlash Storage Card has been powered up with + RESET continuously disconnected or asserted. Operation-After the CompactFlash Storage Card has been configured for I/O operation; this signal is used as interrupt Request. This line is strobe low to generate a pulse mode interrupt or held low for a level mode interrupt In True IDE Mode signal is the active high interrupt Request to the host. This signal is used during Memory Cycles to distinguish between Common Memory and Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory. I 44 The signal must also be active (low) during I/O Cycles when the I/O address is on the Bus. In True IDE Mode this input signal is not used and should be connected to VCC by the host. When the pin is high, this signal Resets the CompactFlash Storage Card. The CompactFlash Storage Card is Reset only at power up if this pin is left high or open from power-up .The CompactFlash Storage Card is also Reset when the Soft Reset bit in the Card Configuration Option Register is set. In the True IDE Mode this input pin is the active low hardware reset from the host. O 37 -IREQ (PC Card I/O Mode) INTRQ (True IDE Mode) -REG (PC Card Memory Mode) -REG (PC Card I/O Mode) -REG (True IDE Mode) RESET (PC Card Memory Mode) RESET (PC Card I/O Mode) I 41 -RESET (True IDE Mode) VCC (PC Card Memory Mode) (PC Card I/O Mode) (True IDE Mode) 13,38 +5V +3.3V power -VS1 / -VS2 (PC Card Memory Mode) (PC Card I/O Mode) (True IDE Mode) -WAIT (PC Card Memory Mode) Voltage O 33,40 Sense Signals. -VS1 is grounded so that the CompactFlash Storage Card CIS can be read at 3.3 volts and -VS2 is reserved by PCMCIA for a secondary voltage. The -WAIT signal is driven low by the CompactFlash Storage Card to signal the host to delay completion of a memory or I/O cycle that is in progress. -WAIT (PC Card I/O Mode) IORDY (True IDE Mode) O 42 In True IDE Mode this output signal may be used as IORDY This is a signal driven by the host and used for strobing memory -WE (PC Card Memory Mode) I 36 write data to the registers of the CompactFlash Storage Card when the card is configured I the memory interface mode. It is also used for writing the configuration registers. -WE (PC Card I/O Mode) In PC Card I/O Mode, this signal is used for writing the configuration registers. 2002-10-20 8/48 Preliminary Signal Name -WE (True IDE Mode) WP (PC Card Memory Mode ) THNCFXXXMBA/BAI Series Description Dir Pin No. In True IDE Mode this input signal is not used and should be connected to VCC by the host. Memory Mode-The CompactFlash Storage Card does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence. I/O Operation-When the CompactFlash Storage Card is configured for I/O Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A Low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port. -IOIS16 (PC Card I/O Mode) O 24 -IOIS16 (True IDE Mode) In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle. 2002-10-20 9/48 Preliminary Access Specifications THNCFXXXMBA/BAI Series 1. Attribute access specifications When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under the condition of -REG="L" as follows. That region can be accessed by Byte/World/Old-byte modes, which are defined by PC card standard specifications. * Attribute Read Access Mode Mode Standby mode Byte access (8bit) L Word access (16bit) Odd byte access (8bit) Note: X L or H L L H L L L L H H X X L L L H H H High-Z invalid invalid invalid even byte High-Z -REG X L -CE2 H H -CE1 H L A0 X L -OE X L -WE X H D8 to D15 High-Z High-Z D0 to D7 High-Z even byte * Attribute Write Access Mode Mode Standby mode Byte access (8bit) L Word access (16bit) Odd byte access (8bit) Note: L L H L L L L H H X X H H H L L L Don't care Don't care Don't care Don't care even byte Don't care -REG X L -CE2 H H -CE1 H L A0 X L -OE X H -WE X L D8 to D15 Don't care Don't care D0 to D7 Don't care even byte X L or H Write CIS-ROM region is invalid. * Attribute Write Timing Example A0~A10 -REG -CE2/-CE1 -OE -WE D0~D15 Dout Din Read cycle Write cycle 2002-10-20 10/48 Preliminary THNCFXXXMBA/BAI Series 2. Task File register access specifications There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address area. Each case of Task File registers read and write operations is executed under the condition as follows. That area can be accessed by Byte/World/Odd Byte modes, which are defined by PC card standard specifications. (1) I/O address map * Task File Register Read Access Mode (1) Mode Standby mode Byte access (8bit) L Word access (16bit) Odd byte access (8bit) Note: X L or H L L H L L L L H H X X L L L H H H H H H H H H High-Z odd byte odd byte odd byte even byte High-Z -REG X L -CE2 H H -CE1 H L A0 X L -IORD X L -IOWR X H -OE X H -WE X H D8 to D15 High-Z High-Z D0 to D7 High-Z even byte * Task File Register Write Access Mode (1) Mode Standby mode Byte access (8bit) L Word access (16bit) Odd byte access (8bit) Note: X L or H L L H L L L L H H X X H H H L L L H H H H H H Don't care odd byte odd byte odd byte even byte Don't care -REG X L -CE2 H H -CE1 H L A0 X L -IORD X H -IOWR X L -OE X H -WE X H D8 to D15 D0 to D7 Don't care Don't care Don't care even byte * Task File Register Access Timing Example (1) A0~A10 -REG -CE2/-CE1 -IORD -IOWR D0~D15 Dout Din Read cycle Write cycle 2002-10-20 11/48 Preliminary THNCFXXXMBA/BAI Series (2) Memory address map * Task File Register Read Access Mode (2) Mode Standby mode Byte access (8bit) H Word access (16bit) Odd byte access (8bit) Note: X L or H H H H L L L L H H X X L L L H H H H H H H H H High-Z odd byte odd byte odd byte even byte High-Z -REG X H -CE2 H H -CE1 H L A0 X L -OE X L -WE X H -IORD X H -IOWR X H D8 to D15 High-Z High-Z D0 to D7 High-Z even byte * Task File Register Write Access Mode (2) Mode Standby mode Byte access (8bit) H Word access (16bit) Odd byte access (8bit) Note: X L or H H H H L L L L H H X X H H H L L L H H H H H H Don't care odd byte odd byte odd byte even byte Don't care -REG X H -CE2 H H -CE1 H L A0 X L -OE X H -WE X L -IORD X H -IOWR X H D8 to D15 D0 to D7 Don't care Don't care Don't care even byte * Task File Register Access Timing Example (2) A0~A10 -REG -CE2/-CE1 -OE -WE D0~D15 Dout Din Read cycle Write cycle 2002-10-20 12/48 Preliminary THNCFXXXMBA/BAI Series 3. True IDE Mode The card can be configured in a True IDE This card is configured in this mode only when the-OE input signal is asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host. Only I/O operation to the task file and data register is allowed. If this card is configured during power on sequence, data register is accessed in word (16-bit). The card permits 8-bit accessed if the user issues a Set Feature Command to put the device in 8-bit mode. * True IDE Mode Read I/O Function Mode Invalid mode Standby mode Data register access Alternate status access Other task file access Note: X L or H -CE2 L H H L H -CE1 L H L H L A0~A2 X X 0 6H 1~7H -IORD X X L L L -IOWR X X H H H D8 to D15 High-Z High-Z odd byte High-Z High-Z D0 to D7 High-Z High-Z even byte Status out Data * True IDE Mode Write I/O Function Mode Invalid mode Standby mode Data register access Control register access Other task file access Note: X L or H -CE2 L H H L H -CE1 L H L H L A0~A2 X X 0 6H 1~7H -IORD X X H H H -IOWR X X L L L D8 to D15 Don't care Don't care odd byte Don't care odd byte D0 to D7 Don't care even byte Don't care Control in Data * True IDE Mode I/O Access Timing Example A0~A2 -CE -IORD -IOWR -IOIS16 D0~D15 Dout Din Read cycle Write cycle 2002-10-20 13/48 Preliminary Configuration register specifications THNCFXXXMBA/BAI Series This card supports four Configuration registers for the purpose of the configuration and observation of this card. These registers can be used in memory card mode and I/O card mode. In True IDE mode, these registers cannot be used. 1. Configuration Option register (Address 200h) This register is used for the configuration of the card configuration status and for the issuing soft reset to the card. bit7 SRESET Note: initial value bit6 LevIREQ 00H bit5 bit4 bit3 INDEX bit2 bit1 bit0 Name R/W Function Setting this bit to "1", places the card in the reset state (Card Hard Reset). This operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to "0", places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset). Card configuration status is reset and the card internal initialized operation starts when Card Hard Reset is executed, so next access to the card should be the same sequence as the power on sequence. This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode interrupt is selected. This bits is used for select operation mode of the card as follows. SRESET R/W LevlREQ (HOST->) INDEX (HOST->) Note: initial value 00H R/W R/W When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose of Memory card interface recognition. * INDEX bit assignment INDEX bit 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 1 Card mode Memory card I/O card I/O card I/O card Task file register address 0H to FH, 400H to 7FFH xx0H to xxFH 1F0H to 1F7H, 3F6H to 3F7H 170H to 177H, 376H to 377H Mapping mode Memory mapped Contiguous I/O mapped Primary I/O mapped Secondary I/O mapped 2002-10-20 14/48 Preliminary THNCFXXXMBA/BAI Series 2. Configuration and Status register (Address 202h) This register is used for observing the state of the card. bit7 CHGED Note: initial value bit6 SIGCHG 00H bit5 IOIS8 bit4 0 bit3 0 bit2 PWD bit1 INTR bit0 0 Name CHGED (CARD->) R/W Function This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to "1". When CHGED bit R is set to "1", -STSCHG pin is held "L" at the condition of SIGCHG bit set to "1" and the card configured for the I/O interface. This bit is set or reset by the host for enabling and disabling the status-change signal (-STSCHG SIGCHG (HOST->) R/W pin). When the card is configured I/O card interface and this bit is set "1", -STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept "H". The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus (D7 to D0). IOIS8 (HOST->) PWD (HOST->) R/W When this bit is set to "1", the card enters sleep state (Power Down mode). When this bit is reset to "0", the card transfers to idle state (active mode). RRDY/BSY bit on Pin Replacement Register R/W becomes BUSY when this bit is changed. RRDY/BSY will not become Ready until the power state requested has been entered. This card automatically powers down when it is idle and powers back up when it receives a command. INTR (CARD->) R This bit indicates the internal state of the interrupt request. This bit state is available whether I/O card interface has been configured or not. This signal remains true until the condition, which caused the interrupt request, has been serviced. If the -IEN bit in the Device Control Register disables interrupts, this bit is a zero. 2002-10-20 15/48 Preliminary THNCFXXXMBA/BAI Series 3. Pin Replacement register (Address 204h) This register is used for providing the state of -IREQ signal when the card configured I/O card interface. bit7 0 Note: initial value bit6 0 0CH bit5 CRDY/-BSY bit4 0 bit3 1 bit2 1 bit1 RRDY/-BSY bit0 0 Name CRDY/-BSY (HOST->) RRDY/-BSY (HOST->) R/W Function This bit is set to "1" when the RRDY/-BSY bit changes state. The host may also write this bit. R/W R When read, this bit indicates +READY pin states. When written, this bit is used for CRDY/-BSY bit masking. 4. Socket and Copy register (Address 206h) This register is used for identification of the card from the other cards. Host can read and write this register. Host should set this register before this card's Configuration Option register set. bit7 0 Note: initial value bit6 0 00H bit5 0 bit4 DRV# bit3 0 bit2 0 bit1 0 bit0 0 Name DRV# (HOST->) R/W Function These fields are used for the configuration of the plural cards. When host configures the plural cards, written the card's copy number in this field. In this way, host can perform the card's master/slave organization. R/W 2002-10-20 16/48 Preliminary CIS information CIS information of Compact Flash card is defined as follows. Address 000H 002H 004H 006H 008H 00AH 00CH 00EH 010H 012H 014H 016H 018H 01AH 01CH 01EH 020H 022H 024H 026H 028H 02AH 02CH 02EH 030H 032H 034H 036H 038H 03AH 03CH 03EH 040H 042H 044H 046H 048H 04AH 04CH 04EH 050H 052H 054H 056H THNCFXXXMBA/BAI Series Data 01H 03H D9H 01H FFH 1CH 04H 03H D9H 01H FFH 18H 02H DFH 01H 20H 04H 98H 00H 00H 00H 15H 20H 04H 01H 54H 4FH 53H 48H 49H 42H 41H 20H 54H 48H 4EH 43H 46H 30H 30H 30H 4DH 42H 41H Description of contents CISTPL_DEVICE TPL_LINK Device information Device information END MARKER CISTPL_DEVICE_OC TPL_LINK Conditions information Device information Device information END MARKER CISTPL_JEDEC_C TPL_LINK PCMCIA's manufacture's JEDEC ID code PCMCIA's JEDEC device code CISTPL_MANFID TPL_LINK Low byte of manufacturer's ID code High byte of manufacturer's ID code Low byte of product code High byte of product code CISTPL_VERS_1 TPL_LINK TPLLV1_MAJOR TPLLV1_MINOR ` T ' (Vender Specific Strings) ` O ' (Vender Specific Strings) ` S ' (Vender Specific Strings) ` H ' (Vender Specific Strings) ` I ' (Vender Specific Strings) ` B ' (Vender Specific Strings) ` A ' (Vender Specific Strings) ` ' (Vender Specific Strings) CIS function Tuple code Tuple link Tuple data Tuple data End of Tuple Tuple code Tuple link Tuple data Tuple data Tuple data End of Tuple Tuple code Tuple link Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data ` T ' (Vender Specific Strings) ` H ' (Vender Specific Strings) ` N ' (Vender Specific Strings) ` C ' (Vender Specific Strings) ` F ' (Vender Specific Strings) ` 0 ' (Card capacity dependent strings) ` 0 ' (Card capacity dependent strings) ` 0 ' (Card capacity dependent strings) ` M ' (Card capacity dependent strings) ` B ' (Vender Specific Strings) ` A ' (Vender Specific Strings) 2002-10-20 17/48 Preliminary Address 058H 05AH 05CH 05EH 060H 062H 064H 066H 068H 06AH 06CH 06EH 070H 072H 074H 076H 078H 07AH 07CH 07EH 080H 082H 084H 086H 088H 08AH 08CH 08EH 090H 092H 094H 096H 098H 09AH 09CH 09EH 0A0H 0A2H 0A4H 0A6H 0A8H 0AAH 0ACH 0AEH 0B0H 0B2H 0B4H THNCFXXXMBA/BAI Series CIS function Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data End of Tuple Tuple code Tuple link Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Data 20H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH 21H 02H 04H 01H 22H 02H 01H 01H 22H 03H 02H 0CH 0FH 1AH 05H 01H 03H 00H 02H 0FH 1BH 08H C0H C0H A1H 01H 55H 08H 00H 20H 1BH 06H 00H 01H 21H B5H ` ' Description of contents Null Terminator Reserved (Vender Specific Strings) Reserved (Vender Specific Strings) Reserved (Vender Specific Strings) Reserved (Vender Specific Strings) Reserved (Vender Specific Strings) Reserved (Vender Specific Strings) Reserved (Vender Specific Strings) Reserved (Vender Specific Strings) END MARKER CISTPL_FUNCID TPL_LINK IC Card function code System initialization bit mask CISTPL_FUNCE TPL_LINK Type of extended data Function information CISTPL_FUNCE TPL_LINK Type of extended data Function information Function information CISTPL_CONFIG TPL_LINK Size field Index number of last entry Configuration register base address (Low) Configuration register base address (High) Configuration register present mask CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Interface Descriptor Feature Select Vcc Selection Byte Nom V Parameter Memory length (256 byte pages) Memory length (256 byte pages) Misc features CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Feature Select Vcc Selection Byte Nom V Parameter 2002-10-20 18/48 Preliminary Address 0B6H 0B8H 0BAH 0BCH 0BEH 0C0H 0C2H 0C4H 0C6H 0C8H 0CAH 0CCH 0CEH 0D0H 0D2H 0D4H 0D6H 0D8H 0DAH 0DCH 0DEH 0E0H 0E2H 0E4H 0E6H 0E8H 0EAH 0ECH 0EEH 0F0H 0F2H 0F4H 0F6H 0F8H 0FAH 0FCH 0FEH 100H 102H 104H 106H 108H 10AH 10CH 10EH 110H 112H THNCFXXXMBA/BAI Series CIS function Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Data 1EH 4DH 1BH 0AH C1H 41H 99H 01H 55H 64H F0H FFH FFH 20H 1BH 06H 01H 01H 21H B5H 1EH 4DH 1BH 0FH C2H 41H 99H 01H 55H EAH 61H F0H 01H 07H F6H 03H 01H EEH 20H 1BH 06H 02H 01H 21H B5H 1EH 4DH Description of contents Nom V Parameter Peak I Parameter CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Interface Descriptor Feature Select Vcc Selection Byte Nom V Parameter I/O Parameter IRQ parameter IRQ request mask IRQ request mask Misc features CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Feature Select Vcc Selection Byte Nom V Parameter Nom V Parameter Peak I Parameter CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Interface Descriptor Feature Select Vcc Selection Byte Nom V Parameter I/O parameter I/O range length and size Base address Base address Address length Base address Base address Address length IRQ parameter Misc features CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Feature Select Vcc Selection Byte Nom V Parameter Nom V Parameter Peak I Parameter 2002-10-20 19/48 Preliminary Address 114H 116H 118H 11AH 11CH 11EH 120H 122H 124H 126H 128H 12AH 12CH 12EH 130H 132H 134H 136H 138H 13AH 13CH 13EH 140H 142H 144H 146H 148H 14AH THNCFXXXMBA/BAI Series CIS function Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link End of Tuple Data 1BH 0FH C3H 41H 99H 01H 55H EAH 61H 70H 01H 07H 76H 03H 01H EEH 20H 1BH 06H 03H 01H 21H B5H 1EH 4DH 14H 00H FFH Description of contents CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Interface Descriptor Feature Select Vcc Selection Byte Nom V Parameter I/O parameter I/O range length and size Base address Base address Address length Base address Base address Address length IRQ parameter Misc features CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Feature Select Vcc Selection Byte Nom V Parameter Nom V Parameter Peak I Parameter CISTPL_NO_LINK TPL_LINK CISTPL_END 2002-10-20 20/48 Preliminary Task File Register specification THNCFXXXMBA/BAI Series These registers are used for reading and writing the storage data in this card. These registers are mapped five types by the configuration of INDEX in Configuration Option register. The decoded addresses are shown as follows. Memory map (INDEX=0) -REG 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A9~A4 X X X X X X X X X X X X X X X A3 0 0 0 0 0 0 0 0 1 1 1 1 1 X X A2 0 0 0 0 1 1 1 1 0 0 1 1 1 X X A1 0 0 1 1 0 0 1 1 0 0 0 1 1 X X A0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H DH EH FH 8H 9H -OE=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Dup. Even data register Dup.odd data register Dup.error register Alt. status register Drive address register Even data register Odd data register -WE=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Dup. even data register Dup.odd data register Dup.feature register Device control register Reserved Even data register Odd data register Contiguous I/O map (INDEX=1) -REG 0 0 0 0 0 0 0 0 0 0 0 0 0 A10~A4 X X X X X X X X X X X X X A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 1 0 1 Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H DH EH FH -OE=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Dup. even data register Dup.odd data register Dup.error register Alt. status register Drive address register -WE=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Dup. even data register Dup.odd data register Dup.feature register Device control register Reserved 2002-10-20 21/48 Preliminary THNCFXXXMBA/BAI Series Primary I/O map (INDEX=2) -REG 0 0 0 0 0 0 0 0 0 0 A10 X X X X X X X X X X A9~A4 1FH 1FH 1FH 1FH 1FH 1FH 1FH 1FH 3FH 3FH A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved Secondary I/O map (INDEX=3) -REG 0 0 0 0 0 0 0 0 0 0 A10 X X X X X X X X X X A9~A4 17H 17H 17H 17H 17H 17H 17H 17H 37H 37H A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved True IDE Mode I/O map -CE2 1 1 1 1 1 1 1 1 0 0 -CE1 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved 2002-10-20 22/48 Preliminary THNCFXXXMBA/BAI Series 1. Data register This register is a 16-bit register that has read/write ability, and it is used for transferring 1 sector data between the card and the host. This register can be accessed in word mode and byte mode. This register overlaps the Error or Feature register. bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D0 to D15 2. Error register This register is a read only register, and it is used for analyzing the error content at the card accessing. register is valid when the BSY bit in Status register and Alternate Status register are set to "0"(Ready). This bit7 BBK bit6 UNC bit5 0 bit4 IDNF bit3 0 bit2 ABRT bit1 0 bit0 AMNF bit 7 6 4 2 0 Name BBK(Bad Block detected) UNC(Data ECC error) IDNF(ID Not Found) ABRT(ABoRTed command) AMNF(Address Mark Not Found) Function This bit is set when a Bad Block is detected in requester ID field. This bit is set when Uncorrectable error is occurred at reading the card. The requested sector ID is in error or cannot be found. This bit is set if the command has been aborted because of the card status condition.(Not ready, Write fault, Invalid command, etc.) This bit is set in case of a general error. 3. Feature register This register is write-only register, and provides information regarding features of the drive that the host wishes to utilize. bit7 bit6 bit5 bit4 bit3 Feature byte bit2 bit1 bit0 4. Sector count register This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the card. If the value of this register is zero, a count of 256 sectors is specified. In plural sector transfer, if not successfully completed, the register contains the number of sectors, which need to be transferred in order to complete, the request. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Sector count byte 5. Sector number register This register contains the starting sector number, which is started by following sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Sector number byte 2002-10-20 23/48 Preliminary THNCFXXXMBA/BAI Series 6. Cylinder low register This register contains the low 8-bit of the starting cylinder address, which is started by following sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Cylinder low byte 7. Cylinder high register This register contains the high 8-bit of the starting cylinder address, which is started by following sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Cylinder high byte 8. Drive head register This register is used for selecting the Drive number and Head number for the following command. bit7 Obsolete bit6 LBA bit5 Obsolete bit4 DRV bit3 Head number bit2 bit1 bit0 bit 7 6 Obsolete LBA Name This bit is normally set to "1". Function LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address (LBA) mode. When LBA = 0, CHS mode is selected. When LBA=1, LBA mode is selected. In LBA mode, the Logical Block Address is interrupted as follows: LBA07~LBA00Sector Number Register D7 to D0. LBA15~LBA08Cylinder Low Register D7 to D0. LBA23~LBA16Cylinder High Register D7 to D0. LBA27~LBA24Drive / Head Register bits HS3 to HS0. 5 Obsolete This bit is normally set to "1". This bit is used for selecting the Master (Card 0) and Slave (Card 1) in Master/Slave organization. The card is set to be Card 0 or 1 by using DRV# of the Socket and Copy register. This bit is used for selecting the Head number for the following command. Bit 3 is MSB. 4 DRV (Drive select) 3 Head number 2002-10-20 24/48 Preliminary THNCFXXXMBA/BAI Series 9. Status register This register is read only register, and it indicates the card status of command execution. When this register is read in configured I/O card mode (INDEX=1,2,3) and level interrupt mode, -IREQ is negated. bit7 BSY bit6 DRDY bit5 DWF bit4 DSC bit3 DRQ bit2 CORR bit1 IDX bit0 ERR bit 7 BSY (BuSY) Name Function This bit is set when the card internal operation is executing. When this bit is set to "1", other bits in this register are invalid. If this bit and DSC bit are set to "1", the card is capable of receiving the read or write or seek requests. If this bit is set to "0", the card prohibits these requests. This bit is set if this card indicates the write fault status. This bit is set when the drive seeks complete. This bit is set when the information can be transferred between the host and Data register. This bit is cleared when the card receives the other command. This bit is set when a correctable data error has been occurred and the data has been corrected. This bit is always set to "0". This bit is set when the previous command has ended in some type of error. The error information is set in the error register. This bit is cleared by the next command. 6 5 4 3 DRDY (Drive ReaDY) DWF (Drive Write Fault) DSC (Drive Seek Complete) DRQ (Data ReQuest) 2 1 CORR (CORRected data) IDX (InDeX) 0 ERR (ERRor) 10. Alternate status register This register is the same as Status register in physically, so the bit assignment refers to previous item of Status register. But this register is different from Status register that -IREQ is not negated when data read. 11. Command register This register is write only register, and it is used for writing the command to execute the requested operation. The command code is written in the command register, after the parameter is written in the Task File when the card is in Ready state. 2002-10-20 25/48 Preliminary THNCFXXXMBA/BAI Series Used parameter Command Command code FR Check power mode Execute drive diagnostic Erase sector Format track Identify Drive Idle Idle immediate Initialize drive parameters Read buffer Read multiple Read long sector Read sector Read verify sector Recalibrate Request sense Seek Set features Set multiple mode Set sleep mode Stand by Stand by immediate Translate sector Wear level Write buffer Write long sector Write multiple Write multiple w/o erase Write sector Write sector w/o erase Write verify E5H or 98H 90H C0H 50H ECH E3H or 97H E1h or 95h 91H E4H C4H 22H or 23H 20H or 21H 40h or 41h 1Xh 03H 7XH EFH C6H E6h or 99h E2h or 96h E0h or 94h 87H F5H E8H 32h or 33h C5H CDH 30H or 31H 38H 3CH N N N N N N N N N N N N N N N N Y N N N N N N N N N N N N N SC N N Y Y N Y N Y N Y N Y Y N N N N Y N N N Y N N N Y Y Y Y Y SN N N Y N N N N N N Y Y Y Y N N Y N N N N N Y N N Y Y Y Y Y Y CY N N Y Y N N N N N Y Y Y Y N N Y N N N N N Y N N Y Y Y Y Y Y DR Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y HD N N Y Y N N N Y N Y Y Y Y N N Y N N N N N Y Y N Y Y Y Y Y Y LBA N N Y Y N N N N N Y Y Y Y N N Y N N N N N Y N N Y Y Y Y Y Y Notes: FR: Feature register SC: Sector Count register SN: Sector Number register CY: Cylinder register DR: DRV bit of Drive Head register HD: Head Number of Drive Head Supported Y: The register contains a valid parameter for this command. N: The register does not contain a valid parameter for this command. 2002-10-20 26/48 Preliminary THNCFXXXMBA/BAI Series 12. Device control register This register is write only register, and it is used for controlling the card interrupt request and issuing an ATA soft reset to the card. bit7 X bit6 X bit5 X bit4 X bit3 1 bit2 SRST bit1 nIEN bit0 0 bit 7 to 4 3 Name X 1 Don't care This bit is set to "1". Function 2 SRST(Software ReSeT) This bit is set to "1" in order to force the card to perform Task File Reset operation. This does not change the Card Configuration registers as a Hardware Reset does. The card remains in Reset until this bit is reset to "0". This bit is used for enabling -IREQ. When this bit is set to "0", -IREQ is enabled. When this bit is set to "1", -IREQ is disabled. This bit is set to "0". 1 0 nIEN(Interrupt Enable) 0 13. Drive Address register This register is read only register, and it is used for confirming the drive status. This register is provides for compatibility with the AT disk drive interface. It is recommended that this register is not mapped into the host's I/O space because of potential conflicts on bit7. bit7 X bit6 nWTG bit5 nHS3 bit4 nHS2 bit3 nHS1 bit2 nHS0 bit1 nDS1 bit0 nDS0 bit 7 6 5 to 2 1 0 Name X nWTG (WriTing Gate) nHS3 to nHS0 (Head Select3-0) nDS1 (Idrive Select1) nDS0 (Idrive Select0) Function This bit remains tri-state when host read access. This bit is set as 0 These bits are the negative value of Head Select bits (bit3 to 0) in Drive/Head register. This bit is 0 when drive 1 is active and selected. This bit is 0 when drive 0 is active and selected. 2002-10-20 27/48 Preliminary ATA Command specifications THNCFXXXMBA/BAI Series This table summarizes the ATA command set with the paragraphs. Following shows the supported commands and command codes, which are written in command registers. ATA Command Set No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Command set Check power mode Execute drive diagnostic Erase sector(s) Format track Identify Drive Idle Idle immediate Initialize drive parameters Read buffer Read multiple Read long sector Read sector (s) Read verify sector (s) Recalibrate Request sense Seek Set features Set multiple mode Set sleep mode Stand by Stand by immediate Translate sector Wear level Write buffer Write long sector Write multiple Write multiple w/o erase Write sector Write sector w/o erase Write verify Code E5h or 98h 90H C0H 50H ECH E3h or 97h E1h or 95h 91H E4H C4H 22H or 23H 20H or 21H 40H or 41H 1XH 03H 7XH EFH C6H E6h or 99h E2h or 96h E0h or 94h 87H F5H E8H 32H or 33H C5H CDH 30H or 31H 38H 3CH FR Y SC Y Y Y Y Y Y Y Y Y Y Y Y Y Y SN Y Y Y Y Y Y Y Y Y Y Y Y Y CY Y Y Y Y Y Y Y Y Y Y Y Y Y Y DR Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y HD Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y LBA Y Y Y Y Y Y Y Y Y Y Y Y Y Y Notes: FR: Feature register SC: Sector Count register (00H~FFH) SN: Sector Number register (01H~20H) CY: Cylinder Low / High register DR: Drive bit of Drive / Head register HD: Head No.(0~3) of Drive / Head register LBA: Logical Block Address Mode supported Y: Set up : Not set up 2002-10-20 28/48 Preliminary (1) (2) (3) (4) THNCFXXXMBA/BAI Series Check Power Mode (code: E5h or 98h): This command checks the power mode. Execute Drive Diagnostic (code: 90h): This command performs the internal diagnostic tests implemented by the Card. Erase Sector(s)(code: C0h): This command is used to erase data sectors. Format Track (code: 50h): This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically FFh or 00h). To remain host backward compatible, the card expects one sector (512Bytes) of data from the host to follow the command with same protocol as the Write Sector Command. Identify Drive (code: ECh): This command enables the host to receive parameter information from the Card. Identify Drive Information Word address 0 1 2 3 4 5 6 7 to 8 9 10 to 19 20 21 22 23 to 46 47 48 49 50 51 52 53 to 58 59 60 to 61 62 to 255 Default value 848AH XXXX 0000H 00XXH 0000H XXXX XXXX XXXX 0000H XXXX 0001H 0004H 0004H XXXX 0001H 0000H 0200H 0000H 0200H 0000H XXXX 0101H XXXX 0000H Total bytes 2 2 2 2 2 2 2 4 2 20 2 2 2 48 2 2 2 2 2 2 12 2 4 388 Data field type information General configuration bit-significant information Default number of cylinders Reserved Default number of heads Number of unformatted bytes per track Number of unformatted bytes per sector Default number of sectors per track Number of sectors per card(Word7=MSW,Words=LSW) Reserved Serial number in ASCII Buffer type (single ported) Buffer size in 512 byte increments # of ECC bytes passed on Read/Write Long Commands Firmware revision in ASCII etc. Maximum of 1 sector on Read/Write Multiple command Double Word not supported Capabilities: DMA NOT Supported(bit 8), LBA supported (bit9) Reserved PIO data transfer cycle timing mode 2 DMA data transfer cycle timing mode not Supported Reserved Multiple sector setting is valid Total number of sectors addressable in LBA Mode Reserved (5) (6) Idle (code: E3h or 97h): This command causes the Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the sector count is zero, the automatic power mode is disabled. Idle Immediate (code: E1h or 95h): This command causes the Card to set BSY, enter the Idle(Read) mode, clear BSY and generate an interrupt. Initialize Drive Parameters (code: 91h): This command enables the host to set the number of sectors per track and the number of heads per cylinder. Read Buffer (code: E4h): This command enables the host to read the current contents of the card's sector buffer. Read Multiple (code: C4h): This command performs similarly to the Read Sectors command. Interrupts are not generated on each sector, but on the transfer of a block, which contains the number of sectors defined by a Set Multiple command. (7) (8) (9) (10) 2002-10-20 29/48 Preliminary (11) (12) THNCFXXXMBA/BAI Series Read Long Sector (code 22h or 23h): This command performs similarly to the Read Sector(s) command except that it returns 516 bytes of data instead of 512 bytes. Read Sector(s) (code 20h or 21h): This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer beings specified in the Sector Number register. Read Verify Sector(s) (code: 40h or 41h): This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. Recalibrate (code: 1Xh): This command is effectively a NOP command to the Card and is provided for compatibility purposes. Request Sense (code: 03h): This command requests an extended error code after command ends with an error. Seek (code: 7Xh): This command is effectively a NOP command to the Card although it does perform a range check. Set Features (code: EFh): This command is used by the host to establish or select certain features. Features 01H 55H 66H 81H BBH CCH Enable 8-bit data transfers. Disable Read Look Ahead. Disable Power on Reset (POR) establishment of defaults at Soft Reset. Disable 8-bit data transfers. 4 bytes of data apply on Read/Write Long commands. Enable Power on Reset (POR) establishment of defaults at Soft Reset. Operation (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) Set Multiple Mode (code: C6h): This command enables the Card to perform Read and Write Multiple operations and establishes the block count for these commands. Set Sleep Mode (code: E6h or 99h): This command causes the Card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Stand By (code: E2h or 96h): This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Stand By Immediate (code: E0h or 94h): This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Translate Sector (code: 87h): This command allows the host a method of determining the exact number of times a use sector has been erased and programmed. Wear Level (code: F5h): This command effectively a NOP command and only implemented for backward compatibility. The Sector Count Register will always be returned with a 00h indicating Wear Level is not needed. Write Buffer (code: E8h): This command enables the host to overwrite contents of the Card's sector buffer with any data pattern desired. Write Long Sector (code: 32h or 33h): This command is provided for compatibility purposes and is similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes. Write Multiple (code: C5h): This command is similar to the Write Sectors command. Interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set Multiple command. Write Multiple without Erase (code: CDh): This command is similar to the Write Multiple command with the exception that an implied erase before write operation is not performed. Write Sector(s): (code: 30h or 31h): This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. Write Sector(s) without Erase (code: 38h): This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. Write Verify (code: 3Ch): This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written. (24) (25) (26) (27) (28) (29) (30) 2002-10-20 30/48 Preliminary Sector Transfer Protocol THNCFXXXMBA/BAI Series 1. Sector read: Sector read procedure after the card configured I/O interface is shown as follows. start I/O Access, INDEX=1 Set the cylinder low/high register Set the head No. of drive head register (1) Set the logical sector number Set the sector number register Set in sector count register Set "20h" in command register (2) Set read sector command N Read the status register N "51h"? "58h"? Y Y (3) Polling until ready Read 256 times the data register (512 bytes) (4) Burst data transfer error handle Get all data Y Wait the command input N (5) Read more sectors? (1) A0~A10 -CE1 -CE2 -IOWR -IORD D0~D15 -IREQ 4H 5H 6H 3H 2H (2) 7H 7H (3) 7H 0H (4) 0H 7H (5) 7H 01H 20H D0H58H (Data transfer) D0H50H 2002-10-20 31/48 Preliminary THNCFXXXMBA/BAI Series 2. Sector write: write sector procedure after the card configured I/O interface is shown as follows. start I/O Access, INDEX=1 Set the cylinder low/high register Set the head No. of drive head register (1) Set the logical sector number Set the sector number register Set in sector count register Set "30h" in command register (2) Set write sector command N N Read the status register "51h"? "58h"? Y (3) Polling until ready Read 256 times the data register (512 bytes) (4) Burst data transfer Y N all data Y N Read the status register "51h"? Y N "50h"? Y Wait the command input (5) Read the Status Register Error handle (1) A0~A10 -CE1 -CE2 -IOWR -IORD D0~D15 -IREQ 4H 5H 6H 3H 2H (2) 7H 7H (3) 7H 0H (4) 0H 7H (5) 7H 01H 30H D0H 58H (Data transfer) D0H50H 2002-10-20 32/48 Preliminary Card System performance ITEM Set up times (Reset to Ready) Set up times (Sleep to Idle) Set up times (Deep Power Down to Idle) Data transfer rate to / from host Sustained read transfer rate Sustained write transfer rate Sustained write transfer rate Controller overhead (Command to DRQ) Data transfer cycle end to ready (Sector write) Notes: THNCFXXXMBA/BAI Series Performance 400 ms (max.) 100s (max.) 4 ms (max.) 16.6 M byte / s burst (max.), theoretically 6.5 M byte / s (max.), actually *2 1.5 M byte / s (max.) <8MB~48MB>, actually *2 3.2 M byte / s (max.) <64MB~512MB>, actually *2 4 ms (max.) 500s (typ.), 50ms (max.) *1 1. This parameter will be changed for different capacity and NAND type flash memory, the typical set up time for 2 Giga Bytes flash card is 325ms 2. The actual transfer rate is measured under ATA PIO mode 4 with single cycle time as 120ns. ELECTRICAL SPECIFICATION SYMBOL PARAMETER MIN -0.3 -0.6 4.5 3.0 0 Topr Operating Temperature -40 -20 -45 MAX VCC+ 0.3 6.0 5.5 3.6 70 85 85 90 TYP 5.0 3.3 25 UNIT V V V V C C C C Commercial grade *1 Industrial grade *2 Commercial grade *1 Industrial grade *2 NOTES VIN , VOUT All input / output voltage VCC Power Supply Voltage (Absolute Maximum Ratings) Power Supply Voltage (Recommended Operation Condition) VCC Tstg Notes: Storage Temperature 1. THNCFXXXMBA Series (Commercial grade) 2. THNCFXXXMBAI Series (Industrial grade) 2002-10-20 33/48 Preliminary Input Leakage Current Type IxZ IxU IxD Notes: SYMBOL IL RPU1 RPD1 PARAMETER Input leakage current Pull Up Resistor Pull Down Resister CONDIDTION VIH=Vcc / VIL=GND Vcc = 5.0V Vcc = 5.0V MIN -1 50 50 THNCFXXXMBA/BAI Series MAX 1 500 500 TYP UNIT uA k NOTES *1 *1 *1 1. x refers to the characteristics described in section "DC Characteristics ( Input Characteristics)". For example, I1U indicates a pull up resister with a type 1 input characteristics. Output Drive Type Type OTx OZx OPx ONx Notes: 1. x refers to the characteristics described in section "DC Characteristics ( Output Drive Characteristics)". For example, OT1 refers to Totempole output with a type 1 Output drive characteristics. Totempole Tri-State N-P Channel P-Channel only N-Channel only OUTPUT TYPE VALID CONDITIONS IOH & IOL IOH & IOL IOH Only IOL Only NOTES *1 *1 *1 *1 2002-10-20 34/48 Preliminary THNCFXXXMBA/BAI Series DC CHARACTERISTICS (VCC = 3.3 V 0.3V, VCC = 5 V 0.5V) Ta = 0C~70C for THNCFXXXMBA (Commercial grade) Ta = -40C~85C for THNCFXXXMBAI (Industrial grade) SYMBOL ILI ILO -IPU -IPD ICCS PARAMETER Input leakage current Output leakage current Pull-up current (Resistivity) Pull-down current (Resistivity) Sleep mode current Operating current @ 3.3V Write operation ICCO Read operation Operating current @ 5V Write operation Read operation 43 35 mA VCC = 5V operation 38 30 mA VCC = 3.3V operation MIN MAX 1 1 1.5 2.0 43 (75) -48 / (206) 1.0 1.2 TYP. UNIT A A A (k) A (k) mA TEST CONDITIONS VOUT = high impedance VFORCE = 3.3V VFORCE = 0V VCC = 3.3V VCC = 5V Input Characteristics Type SYMBOL VIH 1 VIL PARAMETER Input High Voltage CMOS (5V Tolerance) Input Low Voltage CMOS (5V Tolerance) VIH 2 VIL Input Low Voltage CMOS (3.3V : CMOS VT+ 3 VT5V: TTL) 0.9 0.9 1.0 0.8 1.0 0.8 2.5 2.5 2.3 2.0 V 2.1 2.1 1.2 1.2 2.1 1.8 1.2 1.1 Input High Voltage (3.3V : CMOS 5V: TTL) MIN 2.0 2.0 2.0 2.0 MAX TYP UNIT CONDITION VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V 1.0 1.0 Input High Voltage CMOS with Schmitt trigger (5V Tolerance) Input Low Voltage CMOS with Schmitt trigger (5V Tolerance) Input High Voltage with Schmitt trigger (3.3V : CMOS 5V: TTL) VT+ 4 VT- Input Low Voltage with Schmitt trigger (3.3V : CMOS 5V: TTL) Output Drive Characteristics Type SYMBOL VOH VOL PARAMETER Output High Voltage Output Low Voltage MIN VCC - 0.8 MAX Gnd + 0.4 TYP UNIT CONDITION IOH = -4mA IOL = 4mA 1 V 2002-10-20 35/48 Preliminary THNCFXXXMBA/BAI Series AC CHARACTERISTICS (VCC = 3.3 V 0.3V, VCC = 5 V 0.5V) Ta = 0C~70C for THNCFXXXMBA (Commercial grade) Ta = -40C~85C for THNCFXXXMBAI (Industrial grade) Attribute Memory Read AC Characteristics SYMBOL tCR tA (A) tA (CE) tA (OE) tDIS (CE) tDIS (OE) tEN (CE) tEN (OE) tV (A) tSU (A) PARAMETER Read cycle time Address access time -CE access time -OE access time Output disable time (-CE) Output disable time (-OE) Output enable time (-CE) Output enable time (-OE) Data valid time (A) Address setup time MIN 250 5 5 0 30 MAX 250 250 125 100 100 TYP ns UNIT NOTES Attribute Memory Read Timing tC (R) An tA (A) -REG tSU(A) tA(CE) -CE tEN(CE) tA(OE) -OE tEN (OE) DOUT tDIS(OE) tDIS(CE) tV(A) 2002-10-20 36/48 Preliminary THNCFXXXMBA/BAI Series Attribute Memory Write AC Characteristics SYMBOL tCW tW (WE) tSU (A) PARAMETER Write cycle time Write pulse time Address setup time MIN 250 150 30 80 30 30 MAX TYP ns UNIT NOTES tSU (D-WEH) Data setup time (-WE) tH (D) tREC (WE) Data hold time Write recover time Attribute Memory Read Timing tC (W) An -REG tSU(A) tW (WE) -WE tH(D) tSU(D-WEH) -CE tREC(WE) -OE DIN Data in Valid 2002-10-20 37/48 Preliminary THNCFXXXMBA/BAI Series I/O Access Read AC Characteristics SYMBOL tD (IORD) tH (IORD) tW (IORD) tSUA (IORD) tHA (IORD) tSUCE (IORD) tHCE (IORD) tSUREG (IORD) tHREG (IORD) PARAMETER Data delay after -IORD Data hold following -IORD -IORD pulse width Address setup before -IORD Address hold following -IORD -CE setup before -IORD -CE hold following -IORD -REG setup before -IORD -REG hold following -IORD MIN 0 165 70 20 5 20 5 0 0 MAX 100 45 45 35 35 TYP ns UNIT NOTES tDFINPACK (IORD) -INPACK delay failing from -IORD tDRINPACK (IORD) -INPACK delay rising from -IORD tDFIOIS16 (ADR) tDRIOIS16 (ADR) -IOIS16 delay failing from address -IOIS16 delay rising from address I/O Access Read Timing An tSUA(IORD) tSUREG(IORD) -REG tSUCE(IORD) -CE tW (IORD) -IORD tDRINPACK(IORD) -INPACK tDFINPACK(IORD) tD (IORD) -IOIS16 DOUT tDFIOIS16(ADR) tDRIOIS16(ADR) tHCE(IORD) tHA(IORD) tHREG(IORD) 2002-10-20 38/48 Preliminary THNCFXXXMBA/BAI Series I/O Access Write AC Characteristics SYMBOL tSU (IOWR) tH (IOWR) tW (IOWR) tSUA (IOWR) tHA (IOWR) tSUCE (IOWR) tHCE (IOWR) tSUREG (IORD) tHREG (IOWR) tDFIOIS16 (ADR) tDRIOIS16 (ADR) PARAMETER Data setup before -IOWR Data hold following -IOWR -IOWR pulse width Address setup before -IOWR Address hold following -IOWR -CE setup before -IOWR -CE hold following -IOWR -REG setup before -IOWR -REG hold following -IOWR -IOIS16 delay failing from address -IOIS16 delay rising from address MIN 60 30 165 70 20 5 20 5 0 MAX 35 35 TYP ns UNIT NOTES I/O Access Write Timing An tSUA(IOWR) tSUREG(IOWR) -REG tSUCE(IORD) -CE tW (IOWR) -IOWR tDRIOIS16(ADR) tSU (IOWR) tH (IOWR) -IOIS16 DIN tDFIOIS16(ADR) DIN Valid tHCE(IOWR) tHA(IOWR) tHREG(IOWR) 2002-10-20 39/48 Preliminary THNCFXXXMBA/BAI Series Common Memory Access Read AC Characteristics SYMBOL tA (OE) tDIS (OE) tSU (A) tH (A) tSU (CE) tH (CE) PARAMETER -OE access time Output disable time (-OE) Address setup time Address hold time -CE setup time -OE hold time MIN 30 20 0 20 MAX 125 100 TYP ns UNIT NOTES Common Memory Access Read Timing An tSU (A) -REG tSU(CE) -CE tA(OE) -OE tDIS (OE) DOUT tH (CE) tH (A) 2002-10-20 40/48 Preliminary THNCFXXXMBA/BAI Series Common Memory Access Write AC Characteristics SYMBOL tSU (D-WEH) tH (D) tW (WE) tH (A) tSU (A) tSU (CE) tREC (WE) tH (CE) PARAMETER Data setup time (-WE) Data hold time Write pulse time Address hold time Address setup time -CE setup time Write recover time -CE hold following -WE MIN 80 30 150 20 30 0 30 20 MAX TYP ns UNIT NOTES Common Memory Access Write Timing An tSU (A) -REG tSU(CE) -CE tW (WE) -WE tREC (WE) tH (CE) tH (A) tH (D) DIN Valid DIN 2002-10-20 41/48 Preliminary THNCFXXXMBA/BAI Series True IDE Mode Access Read AC Characteristics SYMBOL tD (IORD) tH (IORD) tW (IORD) tSUA (IORD) tHA (IORD) tSUCE (IORD) tHCE (IORD) tDFIOIS16 (ADR) tSFIOIS16 (ADR) PARAMETER Data delay after -IORD Data hold following -IORD -ORD width time Address setup before -IORD Address hold following -IORD -CE setup before -IORD -CE hold following -IORD -IOIS16 delay falling from address -IOIS16 delay rising from address MIN 0 165 70 20 5 20 MAX 100 35 35 TYP ns UNIT NOTES True IDE Mode Access Read Timing An tSUA (IORD) tSUCE (IORD) -CE tW (IORD) -IORD tD(IORD) -IOIS16 tDFIOIS16 (ADR) DOUT tH (IORD) tDRIOIS16 (ADR) tHA (IORD) tHCE (IORD) 2002-10-20 42/48 Preliminary THNCFXXXMBA/BAI Series True IDE Mode Access Write AC Characteristics SYMBOL tSU (IOWR) tH (IOWR) tW (IOWR) tSUA (IOWR) tHA (IOWR) tSUCE (IOWR) tHCE (IOWR) tDFIOIS16 (ADR) tSFIOIS16 (ADR) PARAMETER Data setup before -IOWR Data hold following- IOWR -IOWR width time Address setup before -IOWR Address hold following -IOWR -CE setup before -IOWR -CE hold following -IOWR -IOIS16 delay falling from address -IOIS16 delay rising from address MIN 60 30 165 70 20 5 20 MAX 35 35 TYP ns UNIT NOTES True IDE Mode Access Write Timing An tSUA (IOWR) tSUCE (IOWR) -CE tW (IOWR) -IORD tDRIOIS16 (ADR) -IOIS16 tDFIOIS16 (ADR) DOUT tSU (IOWR) tH (IOWR) tHA (IOWR) tHCE (IOWR) 2002-10-20 43/48 Preliminary THNCFXXXMBA/BAI Series Reset Characteristics (only Memory Card Mode or I/O Card Mode) SYMBOL tSU (RESET) tREC (VCC) tPR tPF tW (RESET) tH (Hi-ZRESET) tS (Hi-ZRESET) Reset pulse width PARAMETER Reset setup time -CE recover time VCC rising up time VCC falling down time MIN 100 1 0.1 3 10 1 0 MAX 100 300 TYP UNIT ms s ms ms s ms ms NOTES Hardware Reset Timing tPR VCC 10% 90% 90% tREC(VCC) tPF 10% -CE1,-CE2 tH(Hi-ZRESET) RESET High-Z tSU(RESET) tW (RESET) Low tS(Hi-ZRESET) 2002-10-20 44/48 Preliminary THNCFXXXMBA/BAI Series Power on Reset Characteristics Power on reset sequence must need by -PORST at the rising of VCC. SYMBOL tSU (VCC) tPR PARAMETER -CE setup time VCC rising up time MIN 100 0.1 MAX 100 TYP UNIT ms ms NOTES Power on Reset Timing tPR VCC -PORST tSU(VCC) -CE1,-CE2 2002-10-20 45/48 Preliminary Package Dimensions 1.60mm.05 (.063 in.002) 3.30mm.10 (.130 in .004 ) 2x25.78mm.07 (2x1.015 in .003) 2x12.00mm .10 (2x.472 in .004) THNCFXXXMBA/BAI Series 26 1 1.01mm0.7 (.039 in.003) 50 25 1.01mm0.7( .039 in.003) .99mm.05 (.039 in. . 002) 2.44mm.07 (.096 in. 003) 36.40mm.15 (1.433 in. .006) 2.15mm.07 (.085 in. . 003) TOP 2x 3.00mm.07 (2x .118 in. 003) 41.66mm.13(1.640 in. 005) 4XR 0.5mm .1 (4XR.020 in . 004) 42.80mm.10(1.685 in. 004) 0.76mm .07(0.30 in.003) 0.63mm .07(.025 in. 003) Note: The optional notched configuration was shown in the CF Specification Rev.1.0. In Specification Rev. 1.2. The notch was removed for ease of tooling. This optional configuration can be used but it is not recommended. Type CompactFlash Storage Card Dimensions 2002-10-20 46/48 Preliminary Attention for Card Use * * * * * * THNCFXXXMBA/BAI Series * In the reset or power off, the information of all registers is cleared. Notice that the card insertion/removal should not be executed during host is active, if the card is used in True IDE mode. After the card hard reset, soft reset, or power on reset, ATA reset, command applied the card cannot access during +RDY / -BSY pin is "low" level. Flash card can't be operated in this case. Before the card insertion VCC cannot be supplied to the card. After confirmation that -CD1, -CD2 pins are inseted, supply VCC to the card. -OE must be kept at the VCC level during power on reset in memory card mode and I/O card mode. OE must be kept constantly at the GND level in True IDE mode. Do not turn off the power or remove THNCFXXXMBA/BAI Series from the slot before read/write operation is complete. Avoid using THNCFXXXMBA/BAI Series when the battery is low. Power shortage, power failure and/or removal of THNCFXXXMBA/BAI Series from the slot before read/write operation is complete may cause malfunction of THNCFXXXMBA/BAI Series, data loss and/or damage to data. Routine performance of backing-up data (or taking back-up of data) is strongly recommended. 2002-10-20 47/48 Preliminary THNCFXXXMBA/BAI Series RESTRICTIONS ON PRODUCT USE 000707EBA * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 2002-10-20 48/48 |
Price & Availability of THNCFXXXMBA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |